cxl/core/pci: Move reading of control register to immediately before usage
authorForyun Ma <foryun.ma@jaguarmicro.com>
Tue, 4 Jun 2024 03:21:51 +0000 (11:21 +0800)
committerDave Jiang <dave.jiang@intel.com>
Wed, 17 Jul 2024 17:35:08 +0000 (10:35 -0700)
commita0328b397f3339d8d17a6ec356e94b3c110b010c
tree0ae02a46630d221359620c94bacca74fcfb78de3
parent56478475560bde71dd3ef944b5013900272db273
cxl/core/pci: Move reading of control register to immediately before usage

Relocate the reading of the DVSEC control register to immediately
before usage and avoid unnecessary PCI config access from the read
if DVSEC capability check, hdm_count check, or device validity check
results in failure.

Signed-off-by: Foryun Ma <foryun.ma@jaguarmicro.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240604032151.655-1-foryun.ma@jaguarmicro.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/pci.c