irqchip/ocelot: Fix trigger register address
authorSergey Matsievskiy <matsievskiysv@gmail.com>
Wed, 25 Sep 2024 18:44:15 +0000 (21:44 +0300)
committerThomas Gleixner <tglx@linutronix.de>
Wed, 2 Oct 2024 13:11:07 +0000 (15:11 +0200)
commit9e9c4666abb5bb444dac37e2d7eb5250c8d52a45
treed7c7dc2325ef88dc941d5a55588abd1f7d2e5d4c
parent5fd7e1ee09afd1546b92615123d718ad6c8c5baf
irqchip/ocelot: Fix trigger register address

Controllers, supported by this driver, have two sets of registers:

 * (main) interrupt registers control peripheral interrupt sources.

 * device interrupt registers configure per-device (network interface)
   interrupts and act as an extra stage before the main interrupt
   registers.

In the driver unmask code, device trigger registers are used in the mask
calculation of the main interrupt sticky register, mixing two kinds of
registers.

Use the main interrupt trigger register instead.

Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240925184416.54204-2-matsievskiysv@gmail.com
drivers/irqchip/irq-mscc-ocelot.c