riscv, bpf: Try RVC for reg move within BPF_CMPXCHG JIT
authorXiao Wang <xiao.w.wang@intel.com>
Sun, 19 May 2024 05:05:07 +0000 (13:05 +0800)
committerDaniel Borkmann <daniel@iogearbox.net>
Fri, 24 May 2024 15:40:33 +0000 (17:40 +0200)
commit99fa63d9ca60c4c1cc843fde205e4bc6e86b218f
treeb9b2b76672511530c0a304e2b020ea804b333542
parente944fc8152744a41dc62e720995538e48b053bb9
riscv, bpf: Try RVC for reg move within BPF_CMPXCHG JIT

We could try to emit compressed insn for reg move operation during CMPXCHG
JIT, the instruction compression has no impact on the jump offsets of
following forward and backward jump instructions.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20240519050507.2217791-1-xiao.w.wang@intel.com
arch/riscv/net/bpf_jit_comp64.c