drm/i915/gen9: add WaClearFlowControlGpgpuContextSave
authorTim Gore <tim.gore@intel.com>
Wed, 16 Mar 2016 16:13:46 +0000 (16:13 +0000)
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>
Fri, 18 Mar 2016 11:12:29 +0000 (11:12 +0000)
commit950b2aaeea6960561425fc80adfb5b2fc0ac020f
tree021c9a0fa6dfad8e3ca7855207bb0a1bc51f60f9
parent26720ab97feac7153a7b5c3c79cf5d53a8531126
drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

This allows writes to EU flow control registers. Together
with SIP code from the user-mode driver this resolves a
hang seen in some pre-emption scenarios. Note that this
patch is just the kernel mode part of this workaround.

v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h.

Signed-off-by: Tim Gore <tim.gore@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458144826-17269-1-git-send-email-tim.gore@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c