drm/i915/rkl: Add power well support
authorMatt Roper <matthew.d.roper@intel.com>
Mon, 4 May 2020 22:52:13 +0000 (15:52 -0700)
committerLucas De Marchi <lucas.demarchi@intel.com>
Wed, 20 May 2020 15:35:22 +0000 (08:35 -0700)
commit93e2323b5c85a2b7ac4260d720de26ca5d5ad796
treec8516f959d702cb9a08b91deb487a95983d4309e
parent99e2d8bcb88763fe265ca0e99708eb55e1d44455
drm/i915/rkl: Add power well support

RKL power wells are similar to TGL power wells, but have some important
differences:

 * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
 * PG2 no longer exists
 * DDI-C (aka TC-1) moves from PG1 -> PG3
 * PG5 no longer exists due to the lack of a fourth pipe

Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
be programmed as TC-1 and TC-2 even though this platform doesn't have TC
outputs.

Bspec: 49234
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-9-matthew.d.roper@intel.com
drivers/gpu/drm/i915/display/intel_display_power.c
drivers/gpu/drm/i915/display/intel_vdsc.c