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drm/i915/mtl: Fix HDMI/DP PLL clock selection
authorImre Deak <imre.deak@intel.com>
Wed, 13 Dec 2023 22:05:26 +0000 (00:05 +0200)
committerImre Deak <imre.deak@intel.com>
Fri, 15 Dec 2023 07:45:03 +0000 (09:45 +0200)
commit937d02cc79c6828fef28a4d80d8d0ad2f7bf2b62
tree4295f8ef59438b7578175aa9a359831f883650a7tree | snapshot
parent8cd53c6b200e6a4522524e8cf45adc45a35814e1commit | diff
drm/i915/mtl: Fix HDMI/DP PLL clock selection

Select the HDMI specific PLL clock only for HDMI outputs.

Fixes: 62618c7f117e ("drm/i915/mtl: C20 PLL programming")
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231213220526.1828827-1-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)