drm/i915: Try to program PKG_C_LATENCY more correctly
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 24 Jun 2025 17:00:42 +0000 (20:00 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 27 Jun 2025 12:54:19 +0000 (15:54 +0300)
commit9367e41483125c3e257aa861ea79b119c5bfd2ea
tree31458fd3cac2df9fd6b67011a8b12dcd6344ef36
parent4e3f3add4941a5751df05e733ccccf36d05d512c
drm/i915: Try to program PKG_C_LATENCY more correctly

The current PKG_C_LATENCY stuff looks busted in several ways:
- doesn't account for multiple pipes from different commits
  correctly
- WM_LINETIME is in units of 0.125usec, PKG_C_LATENCY wants
  units on 1 usec
- weird VRR state stuff being checked
- use of pointless RMW

Fix it all up. Note that it's still a bit unclear how all this
works, especially how the added_wake_time ties into the flipq
triggers in DMC, and how we need to sequence updates to
PKG_C_LATENCY when enabling/disabling pipes/etc. We may also
need to think what to about the WM1+ disabling and the related
PSR chicken bits when we can use PKG_C_LATENCY for early wake...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-3-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_core.h
drivers/gpu/drm/i915/display/skl_watermark.c