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ARM: dts: socfpga: fix register entry for timer3 on Arria10
authorDinh Nguyen <dinguyen@kernel.org>
Fri, 31 Jul 2020 15:26:40 +0000 (10:26 -0500)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 17 Sep 2020 11:55:25 +0000 (13:55 +0200)
commit91dff93e5584278c23b1e787435210e94369de75
treef665fb01c2d418a73646e4cabab9aa248b246ac6tree
parent1dc746dfc129ac62df219ca95ebc5b0296d68da4commit | diff
ARM: dts: socfpga: fix register entry for timer3 on Arria10

[ Upstream commit 0ff5a4812be4ebd4782bbb555d369636eea164f7 ]

Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm/boot/dts/socfpga_arria10.dtsi diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)