drm/i915/display/tgl: Disable FBC with PSR2
authorUma Shankar <uma.shankar@intel.com>
Tue, 1 Dec 2020 19:04:05 +0000 (00:34 +0530)
committerUma Shankar <uma.shankar@intel.com>
Wed, 2 Dec 2020 13:38:33 +0000 (19:08 +0530)
commit91bd7a441bf03f87fca72517541aa6e79909a624
tree34350c7106326c5a5c467b24ac733a0d599abe1e
parentca3fb8821fbc016c8baa3acbe6e8bf9cab684061
drm/i915/display/tgl: Disable FBC with PSR2

There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.

Bspec: 50422 HSD: 14010260002

v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)

v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
and removed the crtc->config usages, as per Ville's recommendation.

v4: Introduced a variable in fbc state_cache instead of the earlier
plane.visible WA, as suggested by Jose.

v5: Dropped an extra check for fbc in intel_fbc_enable and addressed
review comments by Jose.

v6: Move WA to end of function and added Jose's RB.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201201190406.1752-2-uma.shankar@intel.com
drivers/gpu/drm/i915/display/intel_fbc.c
drivers/gpu/drm/i915/i915_drv.h