RISC-V: Add SBI PMU snapshot definitions
authorAtish Patra <atishp@rivosinc.com>
Sat, 20 Apr 2024 15:17:21 +0000 (08:17 -0700)
committerAnup Patel <anup@brainfault.org>
Mon, 22 Apr 2024 05:43:50 +0000 (11:13 +0530)
commit8f486ced2860e1023d402d20bf8d785b6f040086
treefb6df8e953a136f45e879ab2760f24dbd58f304f
parentc69f9cb0595ff91759b1ff361d19068e16574229
RISC-V: Add SBI PMU snapshot definitions

SBI PMU Snapshot function optimizes the number of traps to
higher privilege mode by leveraging a shared memory between the S/VS-mode
and the M/HS mode. Add the definitions for that extension and new error
codes.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-6-atishp@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/sbi.h