drm/i915: Implement cdclk restrictions based on Azalia BCLK
authorPandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
Tue, 14 Mar 2017 22:45:56 +0000 (15:45 -0700)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Wed, 22 Mar 2017 19:05:11 +0000 (16:05 -0300)
commit8cbeb06dc6b584009d7492c667a3c9a4b96cdefa
tree3d49810e2a09f98375ca222ca4e3bfc204b664b1
parent78cfa580f81e69857815c59c8908aee454726da1
drm/i915: Implement cdclk restrictions based on Azalia BCLK

According to BSpec, "The CD clock frequency must be at least twice the
frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
default. This check is needed because BXT and GLK support cdclk
frequencies less than 192 MHz.

v2: Include other Gen9 platforms too for completeness.(Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489531556-2926-1-git-send-email-dhinakaran.pandiyan@intel.com
drivers/gpu/drm/i915/intel_cdclk.c