drm/i915/display: Consider fractional vdsc bpp while computing m_n values
authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Fri, 10 Nov 2023 10:10:12 +0000 (15:40 +0530)
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Tue, 14 Nov 2023 09:35:22 +0000 (15:05 +0530)
commit87c8812f4b009b5a5d38b1560b45d4a1cc4b24c5
tree398412a10a73ed544b4605aa267baf50315c6405
parent59a266f068b4f9f54c58e4066ac9ee9023ad9232
drm/i915/display: Consider fractional vdsc bpp while computing m_n values

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.

v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).

v2:
Rebase and pass bits_per_pixel in U6.4 format.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-4-ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_dp.c
drivers/gpu/drm/i915/display/intel_dp_mst.c
drivers/gpu/drm/i915/display/intel_fdi.c