drm/i915: Force sync command ordering (Gen6+)
authorBen Widawsky <ben@bwidawsk.net>
Tue, 13 Dec 2011 03:21:58 +0000 (19:21 -0800)
committerKeith Packard <keithp@keithp.com>
Tue, 3 Jan 2012 17:09:44 +0000 (09:09 -0800)
commit84f9f938be4156e4baea466688bd6abae1c9e6ba
tree7d722807e6f9c86db1eb74ae6b2931a3e54140e0
parente2971bdab2b761683353da383c0fd5ac704d1cca
drm/i915: Force sync command ordering (Gen6+)

The docs say this is required for Gen7, and since the bit was added for
Gen6, we are also setting it there pit pf paranoia. Particularly as
Chris points out, if PIPE_CONTROL counts as a 3d state packet.

This was found through doc inspection by Ken and applies to Gen6+;

Reported-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c