ASoC: ssm2602: Add support for CLKDIV2
authorPaweł Anikiel <pan@semihalf.com>
Fri, 14 Apr 2023 14:02:00 +0000 (16:02 +0200)
committerMark Brown <broonie@kernel.org>
Mon, 17 Apr 2023 11:55:55 +0000 (12:55 +0100)
commit8076c586bbc1c62e075e58f41dafdd8b5022b24d
treebb0da1ad3bb43e64e3ef7ea916dee227d6f2de58
parentfc0b096c92918c2ba4d76411ea763fdeb2ef6b0d
ASoC: ssm2602: Add support for CLKDIV2

The SSM260x chips have an internal MCLK /2 divider (bit D7 in register
R8). Add logic that allows for more MCLK values using this divider.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Link: https://lore.kernel.org/r/20230414140203.707729-7-pan@semihalf.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/ssm2602.c