clk: update cached phase to respect the fact when setting phase
authorShawn Lin <shawn.lin@rock-chips.com>
Thu, 8 Mar 2018 06:49:41 +0000 (14:49 +0800)
committerMichael Turquette <mturquette@baylibre.com>
Mon, 12 Mar 2018 01:21:19 +0000 (18:21 -0700)
commit7f95beea36089918335eb1810ddd7ba8cf9d09cc
treeb47461069098a6da89d660de586ff96fc00c47ed
parent7928b2cbe55b2a410a0f5c1f154610059c57b1b2
clk: update cached phase to respect the fact when setting phase

It's found that the final phase set by driver doesn't match that of
the output from clk_summary:

dwmmc_rockchip fe310000.dwmmc: Successfully tuned phase to 346
mmc0: new ultra high speed SDR104 SDIO card at address 0001

cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample
sdio_sample 0        1        0    50000000 0 0

It seems the cached core->phase isn't updated after the clk was
registered. So fix this issue by updating the core->phase if setting
phase successfully.

Fixes: 9e4d04adeb1a ("clk: add clk_core_set_phase_nolock function")
Cc: Stable <stable@vger.kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drivers/clk/clk.c