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phy: uniphier-pcie: Add dual-phy support for NX1 SoC
authorKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Fri, 29 Oct 2021 10:39:05 +0000 (19:39 +0900)
committerVinod Koul <vkoul@kernel.org>
Tue, 23 Nov 2021 05:51:53 +0000 (11:21 +0530)
commit7f1abed4e9a5d0e0f565ae6c74bf258a97fa8f86
tree24515c547ae203c3bf08355466db57742e8b1b16tree | snapshot
parent25bba42f95f6ad22295c5a0204086ace9bff1e4acommit | diff
phy: uniphier-pcie: Add dual-phy support for NX1 SoC

NX1 SoC supports 2 lanes and has dual-phy. Should set appropriate
configuration values to both PHY registers.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1635503947-18250-7-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/socionext/phy-uniphier-pcie.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)