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clk: renesas: r9a09g057: Add reset entry for SYS
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thu, 2 Jan 2025 18:18:38 +0000 (18:18 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 7 Jan 2025 16:00:56 +0000 (17:00 +0100)
commit7e3557b4dd929aee5961417575893a990650e84e
treefcefda83925b9038b03691993948b4f5daa8f301tree
parent7088d2d7e9a58a972d8c07b4d74837f3c524f2f4commit | diff
clk: renesas: r9a09g057: Add reset entry for SYS

Add the missing reset entry for the `SYS` module in the clock driver. The
corresponding core clock entry for `SYS` is already present.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g057-cpg.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)