riscv: misaligned: Add handling for ZCB instructions
authorNylon Chen <nylon.chen@sifive.com>
Fri, 11 Apr 2025 07:38:49 +0000 (15:38 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 18 Apr 2025 17:52:26 +0000 (10:52 -0700)
commit7b30b1b04e0d04e56e848c3b9c2952c30de05af9
treec36ff8e436f48d6951da851f4898125015732d17
parent61a74ad254628ccd9e88838c3c622885dfb6c588
riscv: misaligned: Add handling for ZCB instructions

Add support for the Zcb extension's compressed half-word instructions
(C.LHU, C.LH, and C.SH) in the RISC-V misaligned access trap handler.

Signed-off-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Link: https://lore.kernel.org/r/20250411073850.3699180-2-nylon.chen@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/kernel/traps_misaligned.c