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(parent: 36ce416) | patch
phy: cadence: Sierra: Update single link PCIe register configuration
authorSwapnil Jakhade <sjakhade@cadence.com>
Thu, 23 Dec 2021 06:01:32 +0000 (07:01 +0100)
committerVinod Koul <vkoul@kernel.org>
Mon, 27 Dec 2021 11:05:09 +0000 (16:35 +0530)
commit7a5ad9b4b98cd95f02ec12c895e80bc521fbf9ec
tree55d97e785c13ad680ad237c7e414ad558dafa281tree | snapshot
parent36ce416330da5b27d84af519f61e94b73596a297commit | diff
phy: cadence: Sierra: Update single link PCIe register configuration

Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)