drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal
authorMarijn Suijten <marijn.suijten@somainline.org>
Tue, 6 Apr 2021 21:47:24 +0000 (23:47 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 11 May 2021 12:47:29 +0000 (14:47 +0200)
commit79f701ec9efa85bb6c09800d439c9cb8e6002dcb
treeeb9c078016070071b333a1ff6833808bafc2561d
parent2f5f4cce496e79ffb8a45f27f2c23b52d7999542
drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

[ Upstream commit 2ad52bdb220de5ab348098e3482b01235d15a842 ]

Leaving this at a close-to-maximum register value 0xFFF0 means it takes
very long for the MDSS to generate a software vsync interrupt when the
hardware TE interrupt doesn't arrive.  Configuring this to double the
vtotal (like some downstream kernels) leads to a frame to take at most
twice before the vsync signal, until hardware TE comes up.

In this case the hardware interrupt responsible for providing this
signal - "disp-te" gpio - is not hooked up to the mdp5 vsync/pp logic at
all.  This solves severe panel update issues observed on at least the
Xperia Loire and Tone series, until said gpio is properly hooked up to
an irq.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210406214726.131534-2-marijn.suijten@somainline.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c