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riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
authorE Shattow <e@freeshell.de>
Fri, 2 May 2025 10:30:41 +0000 (03:30 -0700)
committerConor Dooley <conor.dooley@microchip.com>
Thu, 15 May 2025 20:08:27 +0000 (21:08 +0100)
commit724a6718ce216f904192211f71973643f97384ec
treea504f0a3c8dbca9df2e78485c53bc28aa67f982dtree
parent71385a893cea3e3bc752aa75e3e616073cda7889commit | diff
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg

Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/starfive/jh7110-common.dtsi diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)