ASoC: rsnd: more clear ADG clock debug info
authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Fri, 13 Oct 2017 06:03:06 +0000 (06:03 +0000)
committerMark Brown <broonie@kernel.org>
Fri, 13 Oct 2017 10:19:01 +0000 (11:19 +0100)
commit6cba3fa98cdd045e020f096bb8888225d3906895
tree348b9a019fa1be57af73674c7b057aedab730015
parent3a9fa27be507b19107a8b3fe03a67e8145aea88c
ASoC: rsnd: more clear ADG clock debug info

ADG inputs clock from CLK{A,B,C,I} and outputs clock from
CLKOUT{0,1,2,3} which is selected by BRG{A,B}.
Now, ADG is assuming BRGA is for 44100Hz related clocks,
BRGB is for 48000Hz related clocks.

Clock related debug is very difficult/confusable.
This patch cleanups clock related debug info.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sh/rcar/adg.c