ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Fri, 8 Sep 2017 18:42:33 +0000 (21:42 +0300)
committerVineet Gupta <vgupta@synopsys.com>
Wed, 4 Oct 2017 03:36:49 +0000 (20:36 -0700)
commit6afa3bcf1f919c374d4606a7ed8078d3f67dfa90
treea092ec9d4e004b9e11ca97e67444ac0cb119e6e8
parent043d1e729b0fbaf2b69386fe45290b8a9a18a6a9
ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency

DW sdio controller has external ciu clock divider controlled via
register in SDIO IP. Due to its unexpected default value
(it should divide by 1 but it divides by 8)
SDIO IP uses wrong ciu clock and works unstable

So add temporary fix and change clock frequency from 100000000
to 12500000 Hz until we fix dw sdio driver itself.

Fixes SNPS STAR 9001204800

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/boot/dts/hsdk.dts