clk: sunxi: add names for pll5, pll6 parent clocks to factors_data
authorChen-Yu Tsai <wens@csie.org>
Mon, 3 Feb 2014 01:51:39 +0000 (09:51 +0800)
committerEmilio López <emilio@elopez.com.ar>
Mon, 3 Feb 2014 03:24:32 +0000 (00:24 -0300)
commit667f542db542fddc62d1299b17451d7cae84f6e1
tree5a504fecfe45d2f5831202a273694f6ad7ed53d6
parent373d4e6bb8e9611e56cfbefa8d9246b004276791
clk: sunxi: add names for pll5, pll6 parent clocks to factors_data

Some factor clocks, such as the parent clock of pll5 and pll6, have
multiple output names. Add the corresponding names to factors_data
tied to compatible string.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
drivers/clk/sunxi/clk-sunxi.c