iommu/arm-smmu: Fix ATS1* register writes
authorRobin Murphy <Robin.Murphy@arm.com>
Wed, 27 May 2015 16:09:34 +0000 (17:09 +0100)
committerJoerg Roedel <jroedel@suse.de>
Fri, 29 May 2015 09:12:01 +0000 (11:12 +0200)
commit661d962f19c23df492a03f47b583ef6a540d6031
tree9eca1be5103ea249ce297cfdf2adbe718b54dadb
parentba155e2d21f6bf05de86a78dbe5bfd8757604a65
iommu/arm-smmu: Fix ATS1* register writes

The ATS1* address translation registers only support being written
atomically - in SMMUv2 where they are 64 bits wide, 32-bit writes to
the lower half are automatically zero-extended, whilst 32-bit writes
to the upper half are ignored. Thus, the current logic of performing
64-bit writes as two 32-bit accesses is wrong.

Since we already limit IOVAs to 32 bits on 32-bit ARM, the lack of a
suitable writeq() implementation there is not an issue, and we only
need a little preprocessor ugliness to safely hide the 64-bit case.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/arm-smmu.c