iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S
authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Fri, 6 Dec 2024 11:13:35 +0000 (13:13 +0200)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Wed, 11 Dec 2024 19:20:47 +0000 (19:20 +0000)
commit645fb7c22fd8d27c223b0e4abff442632bd9a75a
tree79211fe8c6bc35307337825ad24e7328cb844e19
parent4af77feab3a2d489e2c7390e8d31b2f88d0b3db6
iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S

Add ADC support for the Renesas RZ/G3S SoC. The key features of this IP
include:
- 9 channels, with one dedicated to reading the temperature reported by the
  Thermal Sensor Unit (TSU)
- A different default ADCMP value, which is written to the ADM3 register.
- Different default sampling rates
- ADM3.ADSMP field is 8 bits wide
- ADINT.INTEN field is 11 bits wide

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20241206111337.726244-14-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
drivers/iio/adc/rzg2l_adc.c