net/mlx5: Modify LSB bitmask in temperature event to include only the first bit
authorShahar Shitrit <shshitrit@nvidia.com>
Thu, 13 Feb 2025 09:46:40 +0000 (11:46 +0200)
committerJakub Kicinski <kuba@kernel.org>
Tue, 18 Feb 2025 00:27:38 +0000 (16:27 -0800)
commit633f16d7e07c129a36b882c05379e01ce5bdb542
tree2ab74ce381433c4d2d9292a8a5431f95afe7f2b5
parentb9b72ce0f5f4679fc878ad010658a72f30595118
net/mlx5: Modify LSB bitmask in temperature event to include only the first bit

In the sensor_count field of the MTEWE register, bits 1-62 are
supported only for unmanaged switches, not for NICs, and bit 63
is reserved for internal use.

To prevent confusing output that may include set bits that are
not relevant to NIC sensors, we update the bitmask to retain only
the first bit, which corresponds to the sensor ASIC.

Signed-off-by: Shahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Link: https://patch.msgid.link/20250213094641.226501-4-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/events.c