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dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tue, 17 Jun 2025 15:57:55 +0000 (16:57 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 19 Jun 2025 18:00:55 +0000 (20:00 +0200)
commit62ab7ac5be90392a9ac0955febab778ebf51bc0a
tree391c2f50fd3eba64a896e25853b08c187754c037tree
parent4e591b890afa0cbc3479f3b88fa7dc1d28972761commit | diff
dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID

Add the Peripheral Module Clock L (PCLKL) core clock ID for the RZ/T2H
(R9A09G077) SoC.  This clock is used by peripherals such as IIC, WDT,
and others.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)