dt-bindings: riscv: Add Andes PMU extension description
authorYu Chien Peter Lin <peterlin@andestech.com>
Thu, 22 Feb 2024 08:39:44 +0000 (16:39 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 12 Mar 2024 14:13:17 +0000 (07:13 -0700)
commit61609bf2b29dcb07de3aaad7d6212cc3c341192b
tree1fcb8da15dfd401dede7a27584e48be67b57848e
parentbc969d6cc96a2d0539576ec639f7a2a7dcf757f8
dt-bindings: riscv: Add Andes PMU extension description

Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-9-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/riscv/extensions.yaml