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(parent: efecba3) | patch
phy: qcom-qmp: pcs: Add v6.20 register offsets
authorAbel Vesa <abel.vesa@linaro.org>
Wed, 8 Feb 2023 18:00:12 +0000 (20:00 +0200)
committerVinod Koul <vkoul@kernel.org>
Fri, 10 Feb 2023 16:58:00 +0000 (22:28 +0530)
commit5f705402739c87b682861f8f06751a8218f52065
treece4871fdebdfb66eb13a9b6c75bd19a47d29d30atree | snapshot
parentefecba3c9f076010701143634c6bf9a75b723107commit | diff
phy: qcom-qmp: pcs: Add v6.20 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h [new file with mode: 0644] blob
drivers/phy/qualcomm/phy-qcom-qmp.h diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)