clk: tegra: Fix xusb_hs_src clock hierarchy
authorAndrew Bresticker <abrestic@chromium.org>
Thu, 15 May 2014 00:32:59 +0000 (17:32 -0700)
committerMike Turquette <mturquette@linaro.org>
Fri, 23 May 2014 05:14:52 +0000 (22:14 -0700)
commit5c992afcf8e4f91fac05d39b86c7f7922a50145c
tree349870dc6143624ca62f5cfa2aa9de3460095d20
parent9d61707b1f83324fc30918787cb6ef101997ecbd
clk: tegra: Fix xusb_hs_src clock hierarchy

Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock.  It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M.  Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/tegra/clk-id.h
drivers/clk/tegra/clk-tegra-periph.c
drivers/clk/tegra/clk-tegra114.c
drivers/clk/tegra/clk-tegra124.c
include/dt-bindings/clock/tegra114-car.h
include/dt-bindings/clock/tegra124-car.h