drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

According to C10 VDR Register programming sequence we need set
C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers from
MsgBus.

v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes

Bspec: 68962
Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-5-jouni.hogander@intel.com
(cherry picked from commit 8921dce70d46e3156b5a0b21675f5ac90903d81d)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>