drm/amdgpu: Force order between a read and write to the same address
authorAlex Sierra <alex.sierra@amd.com>
Mon, 20 Nov 2023 17:31:32 +0000 (11:31 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 29 Nov 2023 22:57:33 +0000 (17:57 -0500)
commit4b27a33c3b173bef1d19ba89e0b9b812b4fddd25
tree8460b7e611d20897f7cbaf78d74b223ff11c250c
parent884e9b0827e889a8742e203ccd052101fb0b945d
drm/amdgpu: Force order between a read and write to the same address

Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h