clk: ingenic: Allow divider value to be divided
authorHarvey Hunt <harvey.hunt@imgtec.com>
Mon, 9 May 2016 16:29:52 +0000 (17:29 +0100)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 12 May 2016 21:48:25 +0000 (14:48 -0700)
commit4afe2d1a6ed5cba794aeeaa816e7c97a45167b01
treee88fd50b5e791760c7abb20f01e087c53583fe34
parent5707291c6cada6db7344c90a548d02f427bf376c
clk: ingenic: Allow divider value to be divided

The JZ4780's MSC clock divider registers multiply the clock divider by 2.
This means that MMC devices run at half their expected speed. Add the
ability to divide the clock divider in order to solve this.

Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/ingenic/cgu.c
drivers/clk/ingenic/cgu.h
drivers/clk/ingenic/jz4740-cgu.c
drivers/clk/ingenic/jz4780-cgu.c