KVM: x86/svm/pmu: Add AMD PerfMonV2 support
authorLike Xu <likexu@tencent.com>
Sat, 3 Jun 2023 01:10:57 +0000 (18:10 -0700)
committerSean Christopherson <seanjc@google.com>
Wed, 7 Jun 2023 00:31:44 +0000 (17:31 -0700)
commit4a2771895ca63a055df815be5e307cce8e85308c
treee27fb5669aca01459be7ad6c975ddfec98a91c37
parentfe8d76c1a6f04387953727ee3e63469956e7360d
KVM: x86/svm/pmu: Add AMD PerfMonV2 support

If AMD Performance Monitoring Version 2 (PerfMonV2) is detected by
the guest, it can use a new scheme to manage the Core PMCs using the
new global control and status registers.

In addition to benefiting from the PerfMonV2 functionality in the same
way as the host (higher precision), the guest also can reduce the number
of vm-exits by lowering the total number of MSRs accesses.

In terms of implementation details, amd_is_valid_msr() is resurrected
since three newly added MSRs could not be mapped to one vPMC.
The possibility of emulating PerfMonV2 on the mainframe has also
been eliminated for reasons of precision.

Co-developed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Like Xu <likexu@tencent.com>
[sean: drop "Based on the observed HW." comments]
Link: https://lore.kernel.org/r/20230603011058.1038821-12-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
arch/x86/kvm/pmu.c
arch/x86/kvm/svm/pmu.c
arch/x86/kvm/x86.c