mlx5: Implement SyncE support using DPLL infrastructure
authorJiri Pirko <jiri@nvidia.com>
Wed, 13 Sep 2023 20:49:43 +0000 (21:49 +0100)
committerDavid S. Miller <davem@davemloft.net>
Sun, 17 Sep 2023 10:50:20 +0000 (11:50 +0100)
commit496fd0a26bbf73b6b12407ee4fbe5ff49d659a6d
tree8385b9596a7380ebb349254c91bc30349cdcc6cf
parent09eeb3aecc6c74c9a911396f9ab46b1a41fcd7b8
mlx5: Implement SyncE support using DPLL infrastructure

Implement SyncE support using newly introduced DPLL support.
Make sure that each PFs/VFs/SFs probed with appropriate capability
will spawn a dpll auxiliary device and register appropriate dpll device
and pin instances.

Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlx5/core/Kconfig
drivers/net/ethernet/mellanox/mlx5/core/Makefile
drivers/net/ethernet/mellanox/mlx5/core/dev.c
drivers/net/ethernet/mellanox/mlx5/core/dpll.c [new file with mode: 0644]
include/linux/mlx5/driver.h
include/linux/mlx5/mlx5_ifc.h