drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 17 Jun 2025 17:07:51 +0000 (20:07 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 23 Jun 2025 14:50:00 +0000 (17:50 +0300)
commit42a7bf8aa730606ae89b60c1058c50866f240e5d
tree635de913a50a32079437bf17750fdb5a5151c3b0
parent266907bb491f2bdd731139792b5a5056b6d0a482
drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL

Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock
gating w/a (Wa_16015201720), so don't apply it.

TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
      is actually needed, not seeing anything in the docs about it...

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-2-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_dmc.c