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um: Switch to 4 level page tables on 64 bit
authorBenjamin Berg <benjamin.berg@intel.com>
Thu, 19 Sep 2024 12:45:11 +0000 (14:45 +0200)
committerJohannes Berg <johannes.berg@intel.com>
Thu, 10 Oct 2024 11:37:22 +0000 (13:37 +0200)
commit41ab5fe7471ff38d2909d1c93b88197a89c6a00f
treeea76a3b75fd7d8d2b7a4be194e74081113d0b595tree
parente167cc7a95fe01e228e403ac90090f8613e7d8bccommit | diff
um: Switch to 4 level page tables on 64 bit

The larger memory space is useful to support more applications inside
UML. One example for this is ASAN instrumentation of userspace
applications which requires addresses that would otherwise not be
available.

Signed-off-by: Benjamin Berg <benjamin.berg@intel.com>
Link: https://patch.msgid.link/20240919124511.282088-11-benjamin@sipsolutions.net
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
arch/um/Kconfig diff | blob | blame | history
arch/um/include/asm/page.h diff | blob | blame | history
arch/um/include/asm/pgalloc.h diff | blob | blame | history
arch/um/include/asm/pgtable-3level.h [deleted file] blob | blame | history
arch/um/include/asm/pgtable-4level.h [new file with mode: 0644] blob
arch/um/include/asm/pgtable.h diff | blob | blame | history
arch/um/kernel/mem.c diff | blob | blame | history
arch/x86/um/Kconfig diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)