drm/amd/display: Floor to mhz when requesting dpp disp clock changes to SMU
authorWenjing Liu <wenjing.liu@amd.com>
Tue, 2 Jan 2024 21:06:35 +0000 (16:06 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 15 Jan 2024 23:35:38 +0000 (18:35 -0500)
commit3fc394111ea7f52ba1baf6f78717c42f71099df4
treef41747d9e6efb2ee3d2eaef6ac7b6837f1c97668
parent6c605f44086af24d7ac1867245aa10bb3360c5bf
drm/amd/display: Floor to mhz when requesting dpp disp clock changes to SMU

[Why]
SMU uses discrete dpp and disp clock levels. When we submit SMU request
for clock changes in Mhz we need to floor the requested value from Khz so
SMU will choose the next higher clock level in Khz to set. If we ceil to
Mhz, SMU will have to choose the next higher clock level after the ceil,
which could result in unnecessarily jumpping to the next level.

For example, we request 1911,111Khz which is exactly one of the SMU preset
level. If we pass 1912Mhz, SMU will choose 2150,000 khz. If we pass
1911Mhz, SMU will choose 1911,111kHz, which is the expected value.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h