drm/i915: Fix the pipe state timing mismatch warnings
authorVandita Kulkarni <vandita.kulkarni@intel.com>
Thu, 2 May 2019 15:10:59 +0000 (20:40 +0530)
committerJani Nikula <jani.nikula@intel.com>
Tue, 14 May 2019 07:36:23 +0000 (10:36 +0300)
commit3c23ed13112cbce6a31b30224582169c81f1c91a
tree22062e94dab8dd7823348c7db1ae4aa1a8696799
parentcdd075960215e057f29f4f758be661e2223ba0f6
drm/i915: Fix the pipe state timing mismatch warnings

Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.

v2: Use the existing intel_get_pipe_timings and do the dsi
    specific adjustments in the encoder get_config hook.(Ville, Jani)

v3: Exclude VBLANK and HBLANK registers for dsi transcoder.

v4: Fix the incomplete conditional logic.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1556809862-31203-1-git-send-email-vandita.kulkarni@intel.com
drivers/gpu/drm/i915/icl_dsi.c
drivers/gpu/drm/i915/intel_display.c