dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Thu, 2 Mar 2023 15:52:55 +0000 (16:52 +0100)
committerLinus Walleij <linus.walleij@linaro.org>
Thu, 9 Mar 2023 13:07:15 +0000 (14:07 +0100)
commit3abe84ea065128f5ad1025f2176156dd04b777ee
treef2457b97dd93a30f81b5e5450b27101f768b78cb
parent6cf103bc03f8a915c8b5c8733a0e7404112f88d8
dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg

The description of second IO address is a bit confusing.  It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base.  The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml