clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
authorChen-Yu Tsai <wens@csie.org>
Wed, 3 May 2017 03:13:46 +0000 (11:13 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Sun, 14 May 2017 06:27:17 +0000 (08:27 +0200)
commit38b8f823864707eb1cf331d2247608c419ed388c
tree76a9d4bfc0966e8feda8297c0df5a404ec6e60f9
parent2ea659a9ef488125eb46da6eb571de5eae5c43f6
clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.

Reported-by: Bob Ham <rah@settrans.net>
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: stable@vger.kernel.org # 4.9.x-
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun6i-a31.c