soc: imx: gpcv2: Turn domain->pgc into bitfield
authorMarek Vasut <marex@denx.de>
Tue, 7 Sep 2021 02:38:29 +0000 (04:38 +0200)
committerShawn Guo <shawnguo@kernel.org>
Mon, 4 Oct 2021 07:53:01 +0000 (15:53 +0800)
commit34a01d9ea7c4981e19c9e926f5e293b011ecd5a3
tree7039e6391194c81573b102de786b2cfd861daeee
parent6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f
soc: imx: gpcv2: Turn domain->pgc into bitfield

There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.

Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.

This is a preparatory patch, no functional change.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/soc/imx/gpcv2.c