clk: renesas: Add r8a77470 CPG Core Clock Definitions
authorBiju Das <biju.das@bp.renesas.com>
Wed, 28 Mar 2018 19:26:11 +0000 (20:26 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 16 Apr 2018 11:39:38 +0000 (13:39 +0200)
commit343e64a6c48a6c86552db945d842283eee9f528b
tree9270fc8f956f199c9b1d6cba8a845525d88c23a4
parentcdc749e22925d5b370cb51ace3cace940bd76cb5
clk: renesas: Add r8a77470 CPG Core Clock Definitions

Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
Manual.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
[geert: Use consecutive numbering]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r8a77470-cpg-mssr.h [new file with mode: 0644]