clk: agilex/stratix10/n5x: fix how the bypass_reg is handled
authorDinh Nguyen <dinguyen@kernel.org>
Fri, 11 Jun 2021 02:52:01 +0000 (21:52 -0500)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 14 Jul 2021 14:55:43 +0000 (16:55 +0200)
commit308d01f5255b455e8bf1f1f6ec5ef557c6f994ce
tree03771a4ab77e618cbe575f0c56ea962171de137f
parente582a2f35245de96836a2f18ebc0f2b7caee7a03
clk: agilex/stratix10/n5x: fix how the bypass_reg is handled

commit dfd1427c3769ba51297777dbb296f1802d72dbf6 upstream.

If the bypass_reg is set, then we can return the bypass parent, however,
if there is not a bypass_reg, we need to figure what the correct parent
mux is.

The previous code never handled the parent mux if there was a
bypass_reg.

Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-4-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/socfpga/clk-periph-s10.c