net/mlx5: Align mlx5_irq structure
authorShay Drory <shayd@nvidia.com>
Wed, 16 Jun 2021 15:58:26 +0000 (18:58 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 11 Aug 2021 18:14:31 +0000 (11:14 -0700)
commit211f4f99edc0d2cd909f1a37561573f7b7d9fc42
tree21754cbc589f0ba90f0a5e325bc40932c65ebadd
parent8e792700b994a4b79abe1303eb379bbd1f4212be
net/mlx5: Align mlx5_irq structure

mlx5_irq structure have holes due to incorrect position of fields in it.
Make them naturally align.

pahole output after alignment:
struct mlx5_irq {
        struct atomic_notifier_head nh;                  /*     0    72 */
        /* --- cacheline 1 boundary (64 bytes) was 8 bytes ago --- */
        cpumask_var_t              mask;                 /*    72     8 */
        char                       name[32];             /*    80    32 */
        struct mlx5_irq_pool *     pool;                 /*   112     8 */
        struct kref                kref;                 /*   120     4 */
        u32                        index;                /*   124     4 */
        /* --- cacheline 2 boundary (128 bytes) --- */
        int                        irqn;                 /*   128     4 */

        /* size: 136, cachelines: 3, members: 7 */
        /* padding: 4 */
        /* last cacheline: 8 bytes */

};

Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c