drm/i915: Changes required to enable DSI Video Mode on CHT
authorGaurav K Singh <gaurav.k.singh@intel.com>
Wed, 1 Jul 2015 12:58:52 +0000 (15:58 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 3 Jul 2015 05:39:02 +0000 (07:39 +0200)
commit20dbe1a1cbf3f1f0a6a07581e5b95ae027c9bea0
treec7a72f4556b48dc2e72f037e4587e0ed3abd7a59
parent3c5c6d88855baf9c3b9aa6243a37bb179f5a737e
drm/i915: Changes required to enable DSI Video Mode on CHT

On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct
dividor & ctrl values are written in cck regs for DSI. This patch has
been tested on CHT RVP with 1200 x 1920 panel.

v2 by Jani, rebased on earlier refactoring, original at [1].

[1] http://mid.gmane.org/1431368400-1942-5-git-send-email-rodrigo.vivi@intel.com

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dsi_pll.c