drm/amdgpu: Force order between a read and write to the same address
authorAlex Sierra <alex.sierra@amd.com>
Mon, 20 Nov 2023 17:31:32 +0000 (11:31 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 29 Nov 2023 21:48:59 +0000 (16:48 -0500)
commit20b07b0cb3a0a2fb3a6daf00f645925be77ec80c
tree7e4103975f6ff625d3fbf36d19f6b1b0ccbca60f
parent4b8251e019ea17037667e6d61aa5e66d5b4f51d2
drm/amdgpu: Force order between a read and write to the same address

Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h