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(merge: 00c78a3 af3c6ea)
Merge branch 'pci/controller/dwc'
authorBjorn Helgaas <bhelgaas@google.com>
Wed, 4 Jun 2025 15:50:39 +0000 (10:50 -0500)
committerBjorn Helgaas <bhelgaas@google.com>
Wed, 4 Jun 2025 15:50:39 +0000 (10:50 -0500)
commit20611193be984391b5ec80a372e7f8bbc7c5b07a
treecdd2a305ff46f2c9216fac457c52e973726bb553tree
parent00c78a3c3fc34bf9d781f415d4dec41429457fc6commit | diff
parentaf3c6eacce0c464f28fe0e3d365b3860aba07931commit | diff
Merge branch 'pci/controller/dwc'

- Set PORT_LOGIC_LINK_WIDTH to one lane to make initial link training more
  robust; this will not affect the intended link width if all lanes are
  functional (Wenbin Yao)

* pci/controller/dwc:
  PCI: dwc: Make link training more robust by setting PORT_LOGIC_LINK_WIDTH to one lane
drivers/pci/controller/dwc/pcie-designware.c diff1 | diff2 | blob | history
Linux 6.x block layer and io_uring tree(s)