RISC-V: hwprobe: Add SCALAR to misaligned perf defines
authorEvan Green <evan@rivosinc.com>
Fri, 9 Aug 2024 21:44:44 +0000 (14:44 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 14 Aug 2024 20:13:24 +0000 (13:13 -0700)
commit1f5288874de776412041022607513ffac74ae1a6
treef3c3b563dfbbff5ca7c1986203aac924301dca47
parentc42e2f076769c9c1bc5f3f0aa1c2032558e76647
RISC-V: hwprobe: Add SCALAR to misaligned perf defines

In preparation for misaligned vector performance hwprobe keys, rename
the hwprobe key values associated with misaligned scalar accesses to
include the term SCALAR. Leave the old defines in place to maintain
source compatibility.

This change is intended to be a functional no-op.

Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240809214444.3257596-3-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/arch/riscv/hwprobe.rst
arch/riscv/include/uapi/asm/hwprobe.h
arch/riscv/kernel/sys_hwprobe.c
arch/riscv/kernel/traps_misaligned.c
arch/riscv/kernel/unaligned_access_speed.c